The invention relates to a test circuit arrangement and a method for testing a plurality of electrical components which are coupled to one another.
Such a test circuit arrangement and such a method are known from [1] and [2].
When manufacturing semiconductor components, in particular when manufacturing chips on wafers, there is frequently the problem that, owing to the local arrangement of individual circuit elements on the wafer and owing to different conditions during the manufacture of the wafer, the circuit elements which are of the same type on the wafers have different properties.
A customary electrical circuit element which is used in the field of semiconductor technology is a transistor, in particular an MOS field-effect transistor.
If the MOS field-effect transistors are used in analog circuits, there is often a need for the most precise knowledge possible of the properties of the circuit elements which are manufactured during a specific manufacturing process under predefined manufacturing conditions, and thus for the most precise knowledge possible of their behavior in an analog circuit.
Owing to the abovementioned differences and irregularities during the manufacturing process of a wafer, the transistors even within one chip often have very different properties.
These different properties of the transistors are usually referred to as mismatching of the (MOS) field-effect transistors.
If a circuit designer has no precise knowledge of the properties of the respectively used field-effect transistor, this mismatching, that is to say the different properties of the field-effect transistors in a chip or wafer or of transistors of chips or wafers which have been manufactured under the same manufacturing conditions, give rise to considerable uncertainties, in particular in the design of an analog electrical circuit which contains such field-effect transistors.
For this reason, it is necessary to obtain information on the properties of manufactured field-effect transistors.
In order to determine the properties of the transistors, it is possible to use a test structure on a reference wafer which has also been manufactured under the manufacturing conditions to be examined, and has reference transistors.
The properties determined by means of such a test structure for the field-effect transistor or transistors which have been manufactured under the same manufacturing conditions as the reference wafer with the reference field-effect transistors are made available to the circuit designer who can include these properties in his design of a circuit, as a result of which a more reliable and dependable design of an electrical circuit, in particular an analog circuit, with such field-effect transistors is possible.
Basic principles of what is referred to as mismatching are described in [3] and [4].
The test circuit arrangement known from [1] and [2] has transistors which are to be tested and which are arranged in columns and rows in a matrix. A column decoder and a row decoder are coupled to the transistors to be tested and serve together as an address decoder for selecting the transistor to be respectively tested.
Furthermore, selection transistors for uncoupling or selecting the transistors to be tested are connected between the column decoders and row decoders.
Each transistor to be tested is arranged in a diode circuit, that is to say the gate terminal of the field-effect transistor to be tested is short-circuited to its drain terminal.
The test circuit arrangement described in [1] and [2] is used to determine the large-signal response of the field-effect transistors which are to be tested, which are coupled to one another and are arranged at a xe2x80x9clargexe2x80x9d distance of several mm from one another.
It is not possible to perform automated testing of different electrical components with known test circuit arrangement.
In particular in a test structure of electrical components which are to be tested and which are arranged far apart from one another, for example by several millimeters, parasitic voltage drops, that is to say parasitic effects, occur owing to the electrical connecting lines between the individual electrical components to be tested.
These voltage drops falsify the measurement result and thus the test results, as a consequence of which the results which are provided to a circuit designer for the individual electrical components are imprecise and, in particular when designing analog circuits, said results give rise to unreliable analog circuits which in some cases do not function or lie outside a predefined specification.
In addition, a circuit arrangement with a test circuit is described in [5].
The invention is thus based on the problem of specifying a test circuit arrangement and a method for testing a plurality of electrical components, which test circuit arrangement and method make it possible to test the electrical components to be tested in a more precise and reliable way.
The problem is solved by means of the test circuit arrangement and by means of the method having the features as claimed in the independent patent claims.
A test circuit arrangement for testing a plurality of electrical components has a plurality of electrical components which are to be tested and which are coupled to one another. In addition, an electrical selection unit, coupled to the electrical components to be tested, is provided for selecting at least one electrical component to be tested. A parasitic voltage drop in the test circuit arrangement can be at least partially compensated using a control element which is coupled to the electrical components to be tested.
In a method for testing a plurality of electrical components which are coupled to one another, an electrical selection unit is used to select an electrical component to be tested from the plurality of electrical components to be tested. A test current is conducted through the selected electrical component to be tested or a test voltage is applied to the electrical component to be tested. A measuring current which results from the test current or the test voltage or a resulting measuring voltage is sensed, that is to say measured, and a resulting parasitic voltage drop in the test circuit arrangement is at least partially compensated by means of a control element within the scope of the measurement.
The invention makes it possible for the first time to permit, within the scope of what is known as long-distance mismatching, that is to say within the scope of the testing of electrical components on a wafer over a large distance of several millimeters, automated compensation of interference influences which occur, in particular, as a result of the connecting lines, that is to say the couplings between the components to be tested.
Such a test circuit arrangement is generally arranged along the chips on a reference wafer.
As the entire test structure extends essentially over the entire reference wafer, it is possible to sense changing properties of the electrical components at different positions within the wafer.
In addition, for this reason it is possible to sense changing properties of the electrical components at various positions within a chip.
The invention thus considerably increases the precision of the test results. This leads to significantly improved analog circuits, as they are based on a more reliable description of the properties of the electrical components, said circuits being obtained by means of the electrical components on wafers which have been manufactured according to the same manufacturing method under the same manufacturing conditions as the reference wafer.
Preferred developments of the invention emerge from the dependent claims.
The refinements of the invention described below relate both to the test circuit arrangement and to the method for testing a plurality of electrical components which are coupled to one another.
The electrical components can be:
at least one transistor, in particular
at least one pnp-type bipolar transistor,
at least one npn-type bipolar transistor,
at least one field-effect transistor, in particular an MOS field-effect transistor (for example NMOS field-effect transistor or PMOS field-effect transistor),
generally any type of transistor,
at least one diode,
at least one electrical resistor or else
at least one electrical capacitor.
The electrical components can be arranged in groups of components, each group of components containing the same electrical components. A plurality of groups of components can be arranged in the test circuit arrangement, each group of components being coupled to the electrical selection unit.
The electrical selection unit can have a shift register and a clock generating element for clocking the shift register. The shift register with which the individual couplings, to which the electrical components to be tested are coupled, are addressed can thus easily be used to completely take into account, and thus test, the electrical component which is to be tested within the test circuit arrangement because all the components are executed sequentially by means of the shift register via the connecting lines.
It is to be noted, that alternatively, any desired addressing mechanism can also be provided, for example the selection unit can be formed by means of free addressing registers which are filled by an external control unit with the corresponding addresses of the component to be respectively tested within the plurality of components to be tested.
In one development of the invention there is provision that the control element is an electrical operational amplifier. The inverting input is coupled to a feedback loop, and the non-inverting input of the operational amplifier is coupled to a predefinable potential. The output of the operational amplifier is coupled to a forward coupling. The forward coupling can be coupled to any electrical component to be tested, and also to the feedback loop.
In this way, parasitic voltage drops are produced at the forward coupling, which preferably extends over the entire test circuit arrangement, owing to the xe2x80x9clargexe2x80x9d distances of several millimeters in the region of the integrated circuits. These voltage drops are compensated, and xe2x80x9cautomaticallyxe2x80x9d eliminated, by feeding back the forward coupling to the inverting input of the operational amplifier via the feedback loop. Therefore, on the forward coupling, generally on a part of the couplings between the components to be tested, parasitic effects do not have any influence on a resulting measuring current or a resulting measuring voltage, that is to say generally on the test result which is obtained and which respectively characterizes the selected electrical component.
Very efficient compensation of the parasitic voltage drops on at least part of the connecting lines between the individual electrical components to be tested is thus achieved in a simple and cost-effective way.
In addition, an electric voltmeter may be provided which can be coupled to each component to be tested.
According to a further refinement of the invention, a current source is provided which can be coupled to each electrical component to be tested.
In this context it is to be noted that the following have virtually no falsifying influence on the test result: the electrical voltmeter (owing to its large internal resistance), the high-impedance inverting input of the operational amplifier and the current source (owing to its low resistance).
In order to be able to determine changing properties which result in different directions along the wafer, according to one further refinement of the invention there is provision to arrange at least some of the electrical components to be tested in different orientations, preferably perpendicularly with respect to one another, within the test circuit arrangement.
One exemplary embodiment of the invention is illustrated in the figures and will be explained in more detail below. Of said figures: